An integrated circuit chip is driven by off-chip signals transmitted to the chip on a transmission line from other components in the system or from outside the system. Alternatively, the integrated circuit chip sends signals to other components in the system or outside the system via the transmission line. Typically the transmission line is on a printed circuit board or equivalent. An input/output (I/O) buffer on the chip provides an interface between the circuitry on the chip and the transmission line. The impedance of the I/O buffer ideally matches the impedance of the transmission line. FIG. 1 shows an ideal output buffer drive structure wherein a signal from an output buffer 101 on a semiconductor integrated circuit chip is transmitted to transmission line 102 off-chip. If the signal is a high level signal, then ideal switch S1 is closed and the output signal approaches VDDQ through pull-up resistor R1 of 50 ohms. The 50 ohms pull-up resistor matches the impedance of the transmission line 102, which is also 50 ohms. If the signal is a low level signal, then ideal switch S1 is open and ideal switch S2 is closed, thereby allowing 50 ohm pull-down resistor R2 to pull the output signal down to Vss, the system ground. Again, the impedance of resistor R2 matches the 50 ohm impedance of the transmission line 102.
Often, the output buffer drive structure is part of a programmable input/output structure capable of being configured to either receive or send signals. While the ideal structure in FIG. 1 sends signals from on chip to off-chip through transmission line 102, the structure in FIG. 2 represents an ideal input receiver with parallel termination. When a signal is being received from transmission line 102 by input receiver 201, the impedance of the input receiver ideally matches the impedance of the transmission line. As shown in FIG. 2, the transmission line 102 has a 50 ohm impedance. The input receiver will match that impedance when ideal switches S3 and S4 are simultaneously closed, placing resistors R3 and R4, each of 100 ohms, essentially in parallel for an AC signal. The parallel arrangement of resistors R3 and R4 results in an equivalent 50 ohm impedance associated with the ideal input receiver structure of FIG. 2. The signal received by the input receiver is then passed through input amplifier A1, which receives on one input lead a reference signal equal to one half of the input voltage Vddi (i.e., Vddi/2) and on the other input lead, the signal from the 50 ohm transmission line 102. The input amplifier A1 then amplifies the signal in preparation for the amplified signal to be sent to other circuitry on the integrated circuit chip. The main advantage of perfect matching between the input termination impedance and the transmission line is to minimize or eliminate reflection back along transmission line 102. Any reflection of this type will cause inter-symbol interference (ISI) with the subsequently transferred signal into receiver 201 reducing the worst case signal amplitude, and ultimately the maximum reliable frequency of operation.
Unfortunately, the structures shown in FIGS. 1 and 2 are ideal. In the real world, the impedance of the output buffer drive structure or the input receiver structure never exactly matches the impedance of the transmission line 102. Accordingly, it is desired to have a structure which can be programmably adjusted to match the impedance associated with the transmission line providing a signal to or receiving a signal from the programmable I/O buffer.
Moreover, the design of the I/O buffers on an integrated circuit chip is becoming more crucial as operating frequencies of the systems are increased. Typically, a chip-to-chip connection across a printed circuit board is, at most, a few inches and, for maximum system operating frequency, reflections must be avoided. The design of the I/O buffer must balance a number of conflicting constraints. Among these constraints are the fact that the design must be resistant to electrostatic discharge (typically, the smaller the channel width on the transistor, the more susceptible the transistor is to being destroyed by an electrostatic discharge), while at the same time, the total width must be kept as small as possible to keep down the drain diode capacitance associated with the device. Furthermore, an output device generally has a larger capacitance than an input device because an output device has to provide a stronger signal to the transmission line than the input device has to provide to the chip. Moreover, both the source/channel capacitance and the drain/channel capacitance are of concern in the design of the structure. Typically, to help avoid susceptibility to electrostatic discharge (“ESD”), a 20 micron minimum width is required for each MOS transistor (either a PMOS or an NMOS transistor). Wafer foundries often have minimum channel width requirements of 20 microns. This limits the impedance granularity (i.e., the variation in width of the input termination and output drive transistors), which can be obtained for a fixed length channel in the MOS transistor. Moreover, output devices tend to have thicker oxides and deeper implants than normal internal devices, again reflecting the fact that the output devices have to be more robust to handle extremely high ESD discharge voltages.
Thus, to provide a high speed I/O buffer for today's high speed systems, the buffer must have minimum capacitance, minimum reflections of incoming and outgoing signals, and maximum ESD protection. While the I/O buffer must be as finely granular as possible in the sense of allowing the input impedance and output impedance to be changed in as fine a degree as possible, the granularity is limited by the requirement that the minimum transistor channel width for a given-channel length cannot go below 20 microns.
The HSTL standard for programmable I/O buffers uses an externally applied resistor on a special ZT input pad for the input circuit, and an externally applied resistor on a special ZQ pad for the output circuit to match impedance with the transmission lines. Advantageously, using these external non-temperature sensitive resistors to set the impedance of the input termination and output drive strength avoids the significant variation of impedance with temperature exhibited by the input termination and output drive MOS devices.